Reuse Methodology Manual for System-On-a Chip Designs,9780792385585

Reuse Methodology Manual for System-On-a Chip Designs

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Edition: 2nd
ISBN13: 9780792385585
ISBN10: 0792385586
Format: Hardcover
Pub. Date: 1999-06-01
Publisher(s): KLUWER ACADEMIC PUBLISHERS
List Price: $119.00

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Summary

Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available. Design reuse -- the use of pre-designed and pre-verified cores -- is the most promising opportunity to bridge the gap between available gate-count and designer productivity.

Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no singlemethodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integr

Table of Contents

Foreword xv
Preface to the Second Edition xvii
Acknowledgements xxi
Introduction
1(10)
Goals of This Document
2(2)
Assumptions
3(1)
Definitions
3(1)
Virtual Socket Interface Alliance
4(1)
Design for Reuse: The Challenge
4(3)
Design for Use
5(1)
Design for Reuse
5(1)
Fundamental Problems
6(1)
Design Reuse: A Business Model
7(4)
Changing Roles in SoC Design
7(1)
Retooling Skills for New Roles
7(1)
Sources of IP for SoC Designs
8(1)
Cost Models Drive Reuse
8(1)
How Much Reuse and When
9(2)
The System-on-a-Chip Design Process
11(14)
A Canonical SoC Design
11(1)
System Design Flow
12(6)
Waterfall vs. Spiral
13(2)
Top-Down vs. Bottom-Up
15(2)
Construct by Correction
17(1)
Summary
17(1)
The Specification Problem
18(2)
Specification Requirements
19(1)
Types of Specifications
19(1)
The System Design Process
20(5)
System-Level Design Issues: Rules and Tools
25(28)
The Standard Model
25(4)
Soft IP vs. Hard IP
27(1)
The Role of Full Custom Design in Reuse
28(1)
Design for Timing Closure: Logic Design Issues
29(7)
Interfaces and Timing Closure
29(4)
Synchronous vs. Asynchronous Design Style
33(1)
Clocking
34(1)
Reset
35(1)
Timing Exceptions and Multicycle Paths
36(1)
Design for Timing Closure: Physical Design Issues
36(2)
Floorplanning
36(1)
Synthesis Strategy and Timing Budgets
36(1)
Hard Macros
37(1)
Clock Distribution
37(1)
Design for Verification: Verification Strategy
38(1)
System Interconnect and On-Chip Buses
39(5)
Basic Interface Issues
39(1)
Tristate vs. Mux Buses
40(1)
Reuse Issues and On-Chip Buses
41(1)
IP-to-IP Interfaces
42(1)
Design for Bring-Up and Debug: On-Chip Debug Structures
43(1)
Design for Low Power
44(5)
Lowering the Supply Voltage
44(1)
Reducing Capacitance and Switching Activity
45(3)
Sizing and Other Synthesis Techniques
48(1)
Summary
48(1)
Design for Test: Manufacturing Tests Strategies
49(1)
System Level Test Issues
49(1)
Memory Test
49(1)
Microprocessor Test
49(1)
Other Macros
49(1)
Logic BIST
50(1)
Prerequisites for Reuse
50(3)
Libraries
50(1)
Physical Design Rules
51(2)
The Macro Design Process
53(20)
Design Process Overview
53(5)
Contents of a Design Specification
58(2)
Top-Level Macro Design
60(3)
Top-Level Macro Design Process
60(2)
Activities and Tools
62(1)
Subblock Design
63(3)
Subblock Design Process
63(2)
Activities and Tools
65(1)
Macro Integration
66(3)
Integration Process
66(2)
Activities and Tools
68(1)
Soft Macro Productization
69(4)
Productization Process
69(2)
Activities and Tools
71(2)
RTL Coding Guidelines
73(54)
Overview of the Coding Guidelines
73(1)
Basic Coding Practices
74(13)
General Naming Conventions
74(2)
Naming Conventions for VITAL Support
76(1)
Architecture Naming Conventions
77(1)
Include Headers in Source Files
77(2)
Use Comments
79(1)
Keep Commands on Separate Lines
79(1)
Line Length
79(1)
Indentation
80(1)
Do Not Use HDL Reserved Words
81(1)
Port Ordering
81(1)
Port Maps and Generic Maps
82(1)
VHDL Entity, Architecture, and Configuration Sections
83(1)
Use Functions
84(1)
Use Loops and Arrays
85(1)
Use Meaningful Labels
86(1)
Coding for Portability
87(4)
Use Only IEEE Standard Types
87(1)
Do Not Use Hard-Coded Numeric Values
88(1)
Packages
88(1)
Include Files
89(1)
Avoid Embedding dc_shell Scripts
89(1)
Use Technology-Independent Libraries
89(1)
Coding For Translation (VHDL to Verilog)
90(1)
Guidelines for Clocks and Resets
91(6)
Avoid Mixed Clock Edges
91(2)
Avoid Clock Buffers
93(1)
Avoid Gated Clocks
93(1)
Avoid Internally Generated Clocks
94(1)
Gated Clocks and Low Power Designs
94(2)
Avoid Internally Generated Resets
96(1)
Coding for Synthesis
97(17)
Infer Registers
97(2)
Avoid Latches
99(3)
If you must use a latch
102(1)
Avoid Combinational Feedback
102(1)
Specify Complete Sensitivity Lists
103(2)
Blocking and Nonblocking Assignments (Verilog)
105(2)
Signal vs. Variable Assignments (VHDL)
107(1)
Case Statements versus if-then-else Statements
108(2)
Coding State Machines
110(4)
Partitioning for Synthesis
114(9)
Register All Outputs
114(1)
Locate Related Combinational Logic in a Single Module
115(1)
Separate Modules That Have Different Design Goals
116(2)
Asynchronous Logic
118(1)
Arithmetic Operators: Merging Resources
118(1)
Partitioning for Synthesis Runtime
119(1)
Avoid Point-to-Point Exceptions and False Paths
120(1)
Eliminate Glue Logic at the Top Level
121(1)
Chip-Level Partitioning
122(1)
Designing with Memories
123(2)
Code Profiling
125(2)
Macro Synthesis Guidelines
127(18)
Overview of the Synthesis Problem
127(1)
Macro Synthesis Strategy
128(5)
Macro Timing Budget
128(1)
Subblock Timing Budget
129(1)
Synthesis in the Design Process
129(1)
Subblock Synthesis Process
130(1)
Macro Synthesis Process
130(1)
Wire Load Models
131(1)
Preserve Clock and Reset Networks
131(1)
Code Checking Before Synthesis
132(1)
Code Checking After Synthesis
132(1)
High-Performance Synthesis
133(1)
Classical Synthesis
133(1)
High-Performance Synthesis
134(1)
Tiling
134(1)
RAM and Datapath Generators
134(8)
Memory Design
134(1)
Datapath Design
135(3)
Design Flow Using Module Compiler
138(2)
RAM Generator Flow
140(1)
Design Reuse with Datapath and RAM Compilers
140(2)
Coding Guidelines for Synthesis Scripts
142(3)
Macro Verification Guidelines
145(26)
Overview of Macro Verification
145(7)
Verification Plan
146(1)
Verification Strategy
147(4)
Subblock Simulation
151(1)
Macro Simulation
151(1)
Prototyping
152(1)
Limited Production
152(1)
Inspection as Verification
152(2)
Adversarial Testing
154(1)
Testbench Design
155(14)
Subblock Testbench
155(1)
Macro Testbench
156(3)
Bus Functional Models
159(1)
Automated Response Checking
160(1)
Verification Suite Design
161(5)
Code Coverage Analysis
166(3)
Timing Verification
169(2)
Developing Hard Macros
171(28)
Overview
171(2)
Why and When to use Hard Macros
172(1)
Design Process for Hard vs. Soft Macros
173(1)
Design Issues for Hard Macros
173(6)
Full Custom Design
173(1)
Interface Design
174(1)
Design For Test
175(1)
Clock and Reset
176(1)
Aspect Ratio
177(1)
Porosity
177(1)
Pin Placement
178(1)
Power Distribution
178(1)
The Hard Macro Design Process
179(2)
Block Integration for Hard Macros
181(1)
Productization of Hard Macros
181(5)
Physical Design
181(3)
Verification
184(1)
Models
185(1)
Documentation
185(1)
Model Development for Hard Macros
186(11)
Functional Models
186(8)
Synthesis and Floorplanning Models
194(3)
Porting Hard Macros
197(2)
Macro Deployment: Packaging for Reuse
199(8)
Delivering the Complete Product
199(6)
Soft Macro Deliverables
200(2)
Hard Macro Deliverables
202(2)
The Design Archive
204(1)
Contents of the User Guide
205(2)
System Integration with Reusable Macros
207(22)
Integration Overview
207(1)
Integrating Macros into an SoC Design
208(3)
Problems in Integrating IP
208(1)
Strategies for Managing Interfacing Issues
209(1)
Interfacing Hard Macros to the Rest of the Design
210(1)
Selecting IP
211(2)
Hard Macro Selection
211(1)
Soft Macro Selection
212(1)
Soft Macro Installation
212(1)
Soft Macro Configuration
213(1)
Synthesis of Soft Macros
213(1)
Integrating Memories
213(1)
Physical Design
214(15)
Design Planning to Initial Placement
216(7)
Placement Loop
223(2)
Timing Closure
225(2)
Verifying the Physical Design
227(1)
Summary
228(1)
System-Level Verification Issues
229(24)
The Importance of Verification
229(1)
The Verification Strategy
230(1)
Interface Verification
231(3)
Transaction Verification
231(1)
Data or Behavioral Verification
232(2)
Standardized Interfaces
234(1)
Functional Verification
234(3)
Application-Based Verification
237(3)
FPGA and LPGA Prototyping
238(1)
Emulation Based Testing
239(1)
Silicon Prototyping
239(1)
Gate-Level Verification
240(4)
Sign-Off Simulation
240(2)
Formal Verification
242(1)
Gate-Level Simulation with Unit-Delay Timing
243(1)
Gate-Level Simulation with Full Timing
243(1)
Specialized Hardware for System Verification
244(9)
Accelerated Verification Overview
246(1)
RTL Acceleration
247(1)
Software Driven Verification
248(1)
Traditional In-Circuit Verification
248(1)
Support for Intellectual Property
249(1)
Design Guidelines for Accelerated Verification
249(1)
Testbenches for Emulation
249(4)
Data and Project Management
253(8)
Data Management
253(4)
Reviews Control Systems
253(2)
Bug Tracking
255(1)
Regressing Testing
255(1)
Managing Multiple Sites
256(1)
Archiving
256(1)
Project Management
257(4)
Development Process
257(1)
Functional Specification
257(1)
Project Plan
258(3)
Implementing a Reuse Process
261(16)
Key Steps in Implementing a Reuse Process
261(2)
Managing the Transition to Reuse
263(7)
Barriers to Reuse
263(1)
Key Elements in Reuse-Based Design
263(2)
Key Steps
265(5)
Organizational Issues in Reuse
270(5)
A Combined Solution
272(1)
A Common Problem
272(1)
A Reuse Economy
273(1)
Summary
274(1)
Redesign for Reuse: Dealing with Legacy Designs
275(2)
Recapturing Intent
275(1)
Using the Design As-Is
275(1)
Retiming
276(1)
Tools for Using Legacy Designs
276(1)
Summary
276(1)
Glossary 277(2)
Bibliography 279(2)
Index 281

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