Power Distribution Networks With On-chip Decoupling Capacitors

by Popovich, Mikhail; Mezhiba, Andrey; Friedman, Eby G.

ISBN13: 9780387716008

ISBN10: 0387716009

Format: Hardcover

Pub. Date: 2008-01-01

Publisher(s): Springer Nature

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Summary

Power Distribution Networks with On-Chip Decoupling Capacitors is dedicated to distributing power in high speed, high complexity integrated circuits with power levels exceeding tens of watts and the power supply below a volt. The book provides insight and intuition into the behavior and design of integrated circuit-based power distribution systems. The book has three primary objectives. The first is to describe the impedance characteristics of the overall power distribution system, from the voltage regulator through the printed circuit board and package onto the integrated circuit to the power terminals of the on-chip circuitry. The second is to discuss the inductive characteristics of on-chip power distribution grids and the related circuit behavior of these structures. The third objective is to present design methodologies for effciently placing on-chip decoupling capacitors in nanoscale integrated circuits. Power Distribution Networks with On-Chip Decoupling Capacitors is a reference for professional engineers in the fields of circuits and systems and computer-aided design.

Introduction	p. 1
Evolution of integrated circuit technology	p. 3
Evolution of design objectives	p. 7
The problem of power distribution	p. 10
Deleterious effects of power distribution noise	p. 17
Signal delay uncertainty	p. 17
On-chip clock jitter	p. 17
Noise margin degradation	p. 20
Degradation of gate oxide reliability	p. 20
Book outline	p. 20
Inductive Properties of Electric Circuits	p. 27
Definitions of inductance	p. 28
Field energy definition	p. 28
Magnetic flux definition	p. 30
Partial inductance	p. 35
Net inductance	p. 40
Variation of inductance with frequency	p. 43
Uniform current density approximation	p. 44
Inductance variation mechanisms	p. 45
Simple circuit model	p. 49
Inductive behavior of circuits	p. 52
Inductive properties of on-chip interconnect	p. 54
Summary	p. 58
Properties of On-Chip Inductive Current Loops	p. 59
Introduction	p. 59
Dependence of inductance on line length	p. 60
Inductive coupling between two parallel loop segments	p. 67
Application to circuit analysis	p. 68
Summary	p. 69
Electromigration	p. 71
Physical mechanism of electromigration	p. 72
Electromigration-induced mechanical stress	p. 75
Steady state limit of electromigration damage	p. 76
Dependence of electromigration lifetime on the line dimensions	p. 78
Statistical distribution of electromigration lifetime	p. 81
Electromigration lifetime under AC current	p. 82
Electromigration in novel interconnect technologies	p. 83
Designing for electromigration reliability	p. 85
Summary	p. 86
High Performance Power Distribution Systems	p. 87
Physical structure of a power distribution system	p. 88
Circuit model of a power distribution system	p. 89
Output impedance of a power distribution system	p. 92
A power distribution system with a decoupling capacitor	p. 95
Impedance characteristics	p. 95
Limitations of a single-tier decoupling scheme	p. 99
Hierarchical placement of decoupling capacitance	p. 101
Resonance in power distribution networks	p. 108
Full impedance compensation	p. 114
Case study	p. 116
Design considerations	p. 119
Inductance of the decoupling capacitors	p. 119
Interconnect inductance	p. 120
Limitations of the one-dimensional circuit model	p. 121
Summary	p. 124
Decoupling Capacitance	p. 125
Introduction to decoupling capacitance	p. 126
Historical retrospective	p. 126
Decoupling capacitor as a reservoir of charge	p. 127
Practical model of a decoupling capacitor	p. 129
Impedance of power distribution system with decoupling capacitors	p. 133
Target impedance of a power distribution system	p. 133
Antiresonance	p. 136
Hydraulic analogy of hierarchical placement of decoupling capacitors	p. 140
Intrinsic vs intentional on-chip decoupling capacitance	p. 145
Intrinsic decoupling capacitance	p. 146
Intentional decoupling capacitance	p. 150
Types of on-chip decoupling capacitors	p. 152
Polysilicon-insulator-polysilicon (PIP) capacitors	p. 153
MOB capacitors	p. 155
Metal-insulator-metal (MIM) capacitors	p. 163
Lateral flux capacitors	p. 165
Comparison of on-chip decoupling capacitors	p. 169
On-chip switching voltage regulator	p. 171
Summary	p. 173
On-Chip Power Distribution Networks	p. 175
Styles of on-chip power distribution networks	p. 176
Basic structure of on-chip power distribution networks	p. 176
Improving the impedance characteristics of on-chip power distribution networks	p. 181
Evolution of power distribution networks in Alpha microprocessors	p. 182
Die-package interface	p. 184
Other considerations	p. 189
Summary	p. 191
Computer-Aided Design and Analysis	p. 193
Design flow for on-chip power distribution networks	p. 194
Linear analysis of power distribution networks	p. 199
Modeling power distribution networks	p. 201
Characterizing the power current requirements of on-chip circuits	p. 207
Numerical methods for analyzing power distribution networks	p. 210
Allocation of on-chip decoupling capacitors	p. 217
Charge-based allocation methodology	p. 218
Allocation strategy based on the excessive noise amplitude	p. 220
Allocation strategy based on excessive charge	p. 221
Summary	p. 223
Inductive Properties of On-Chip Power Distribution Grids	p. 225
Power transmission circuit	p. 225
Simulation setup	p. 228
Grid types	p. 228
Inductance versus line width	p. 233
Dependence of inductance on grid type	p. 234
Non-interdigitated versus interdigitated grids	p. 234
Paired versus interdigitated grids	p. 235
Dependence of Inductance on grid dimensions	p. 236
Dependence of inductance on grid width	p. 236
Dependence of inductance on grid length	p. 238
Sheet inductance of power grids	p. 238
Efficient computation of grid inductance	p. 239
Summary	p. 241
Variation of Grid Inductance with Frequency	p. 243
Analysis approach	p. 243
Discussion of inductance variation	p. 245
Circuit models	p. 245
Analysis of inductance variation	p. 248
Summary	p. 250
Inductance/Area/Resistance Tradeoffs	p. 253
Inductance vs. resistance tradeoff under a constant grid area constraint	p. 253
Inductance vs. area tradeoff under a constant grid resistance constraint	p. 258
Summary	p. 260
Scaling Trends of On-Chip Power Distribution Noise	p. 263
Prior work	p. 264
Interconnect characteristics	p. 266
Global interconnect characteristics	p. 268
Scaling of the grid inductance	p. 268
Flip-chip packaging characteristics	p. 269
Impact of on-chip capacitance	p. 271
Model of power supply noise	p. 272
Power supply noise scaling	p. 274
Analysis of constant metal thickness scenario	p. 274
Analysis of the scaled metal thickness scenario	p. 275
ITRS scaling of power noise	p. 277
Implications of noise scaling	p. 281
Summary	p. 282
Impedance Characteristics of Multi-Layer Grids	p. 285
Electrical properties of multi-layer grids	p. 287
Impedance characteristics of individual grid layers	p. 287
Impedance characteristics of multi-layer grids	p. 290
Case study of a two layer grid	p. 292
Simulation setup	p. 293
Inductive coupling between grid layers	p. 293
Inductive characteristics of a two layer grid	p. 297
Resistive characteristics of a two layer grid	p. 298
Variation of impedance with frequency in a two layer grid	p. 300
Design implications	p. 301
Summary	p. 302
Multiple On-Chip Power Supply Systems	p. 305
ICs with multiple power supply voltages	p. 306
Multiple power supply voltage techniques	p. 307
Clustered voltage scaling (CVS)	p. 309
Extended clustered voltage scaling (ECVS)	p. 310
Challenges in ICs with multiple power supply voltages	p. 311
Die area	p. 312
Power dissipation	p. 312
Design complexity	p. 313
Placement and routing	p. 313
Optimum number and magnitude of available power supply voltages	p. 316
Summary	p. 321
On-Chip Power Distribution Grids with Multiple Supply Voltages	p. 323
Background	p. 325
Simulation setup	p. 325
Power distribution grid with dual supply and dual ground	p. 328
Interdigitated grids with DSDG	p. 331
Type I interdigitated grids with DSDG	p. 331
Type II interdigitated grids with DSDG	p. 333
Paired grids with DSDG	p. 335
Type I paired grids with DSDG	p. 336
Type II paired grids with DSDG	p. 337
Simulation results	p. 340
Interdigitated power distribution grids without decoupling capacitors	p. 341
Paired power distribution grids without decoupling capacitors	p. 348
Power distribution grids with decoupling capacitors	p. 349
Dependence of power noise on the switching frequency of the current loads	p. 353
Design implications	p. 356
Summary	p. 358
Decoupling Capacitors for Multi-Voltage Power Distribution Systems	p. 361
Impedance of a power distribution system	p. 363
Impedance of a power distribution system	p. 364
Antiresonance of parallel capacitors	p. 367
Dependence of impedance on power distribution system parameters	p. 368
Case study of the impedance of a power distribution system	p. 371
Voltage transfer function of power distribution system	p. 376
Voltage transfer function of a power distribution system	p. 376
Dependence of voltage transfer function on power distribution system parameters	p. 378
Case study of the voltage response of a power distribution system	p. 381
Overshoot-free magnitude of a voltage transfer function	p. 383
Tradeoff between the magnitude and frequency range	p. 385
Summary	p. 389
On-chip Power Noise Reduction Techniques in High Performance ICs	p. 391
Ground noise reduction through an additional low noise on-chip ground	p. 393
Dependence of ground bounce reduction on system parameters	p. 395
Physical separation between noisy and noise sensitive circuits	p. 396
Frequency and capacitance variations	p. 397
Impedance of an additional ground path	p. 399
Summary	p. 400
Effective Radii of On-Chip Decoupling Capacitors	p. 403
Background	p. 405
Effective radius of on-chip decoupling capacitor based on a target impedance	p. 407
Estimation of required on-chip decoupling capacitance	p. 409
Dominant resistive noise	p. 410
Dominant inductive noise	p. 411
Critical line length	p. 414
Effective radius as determined by charge time	p. 416
Design methodology for placing on-chip decoupling capacitors	p. 422
Model of on-chip power distribution network	p. 422
Case study	p. 425
Design implications	p. 431
Summary	p. 432
Efficient Placement of Distributed On-Chip Decoupling Capacitors	p. 435
Technology constraints	p. 436
Placing on-chip decoupling capacitors in nanoscale ICs	p. 437
Design of a distributed on-chip decoupling capacitor network	p. 440
Design tradeoffs in a distributed on-chip decoupling capacitor network	p. 445
Dependence of system parameters on R[subscript 1]	p. 446
Minimum C[subscript 1]	p. 447
Minimum total budgeted on-chip decoupling capacitance	p. 448
Design methodology for a system of distributed on-chip decoupling capacitors	p. 450
Case study	p. 453
Summary	p. 457
Impedance/Noise Issues in On-Chip, Power Distribution Networks	p. 459
Scaling effects in chip-package resonance	p. 460
Propagation of power distribution noise	p. 463
Local inductive behavior	p. 465
Summary	p. 469
Conclusions	p. 471
Appendices
Mutual Loop Inductance in Fully Interdigitated Power Distribution Grids with DSDG	p. 477
Mutual Loop Inductance in Pseudo-Interdigitated Power Distribution Grids with DSDG	p. 479
Mutual Loop Inductance in Fully Paired Power Distribution Grids with DSDG	p. 481
Mutual Loop Inductance in Pseudo-Paired Power Distribution Grids with DSDG	p. 483
References	p. 485
Index	p. 509
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Power Distribution Networks With On-chip Decoupling Capacitors

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