High Performance Memory Systems,9780387003108

High Performance Memory Systems

by ; ; ; ; ;
ISBN13: 9780387003108
ISBN10: 038700310X
Format: Hardcover
Pub. Date: 2003-11-01
Publisher(s): Springer Verlag
List Price: $84.99

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Summary

The more rapid rate of increase in the speed of microprocessor technology than in memory speeds has created a serious 'memory gap' for computer designers and manufacturers. "High Performance Memory Systems" addresses this issue and examines all aspects of improving the memory system performance of general-purpose programs. Current research highlights from both industry and academia focus on: coherence, synchronization, and allocation; power-awareness, reliability, and reconfigurability; software-based memory tuning; architecture design issues; and workload considerations. Topics and features: *both harware and software approaches to scalability and speed disparities are considered *introductory chapter provides broad examination of high performance memory systems *includes coverage of topics from several important international conferences Edited by leading international authorities in the field, this new work provides a survey from researchers and practitioners on advances in technology, architecture, and algorithms that address scalability needs in multiprocessors and the expanding gap between CPU/network and memory speeds. It is ideally suited to researchers and R &D professionals with interests or practice in computer engineering, computer architecture, and processor architecture.

Table of Contents

Preface vi
1 Introduction to High-Performance Memory Systems
Haldun Hadimioglu, David Kaeli, Jeffrey Kuskin, Ashwini Nanda, and Josep Torrellas
1(10)
1.1 Coherence, Synchronization, and Allocation
1(1)
1.2 Power-Aware, Reliable, and Reconfigurable Memory
2(1)
1.3 Software-Based Memory Tuning
3(2)
1.4 Architecture-Based Memory Tuning
5(2)
1.5 Workload Considerations
7(4)
Part I Coherence, Synchronization, and Allocation
2 Speculative Locks: Concurrent Execution of Critical Sections in Shared-Memory Multiprocessors
José F. Martinez and Josep Torrellas
11(14)
2.1 Introduction
11(1)
2.2 Speculative Locks
12(9)
2.3 Evaluation
21(1)
2.4 Conclusions
22(1)
References
23(2)
3 Dynamic Verification of Cache Coherence Protocols
Jason F. Cantin, Mikko H. Lipasti and James E. Smith
25(18)
3.1 Introduction
25(4)
3.2 Dynamic Verification of Cache Coherence
29(4)
3.3 SMP Coherence Checker Correctness, Coverage, and Specificity
33(1)
3.4 Coherence Checker Overhead
34(4)
3.5 Related Work
38(1)
3.6 Future Work
39(1)
3.7 Conclusions
39(1)
References
40(3)
4 Timestamp-Based Selective Cache Allocation
Martin Karlsson and Erik Hagersten
43(20)
4.1 Introduction
43(1)
4.2 Related Work
44(2)
4.3 Evaluation Methodology
46(1)
4.4 Staging Cache LO
46(2)
4.5 Selective Allocation
48(5)
4.6 Experimental Results
53(1)
4.7 Future Work
54(2)
4.8 Conclusion
56(2)
References
58(5)
Part II Power-Aware, Reliable, and Reconfigurable Memory
5 Power-Efficient Cache Coherence
Craig Saldanha and Mikko H. Lipasti
63(16)
5.1 Introduction
63(1)
5.2 Snoopy Coherence Protocols
64(2)
5.3 Methodology
66(6)
5.4 Directory Protocols
72(3)
5.5 Simulation Results
75(2)
5.6 Conclusion
77(1)
References
78(1)
6 Improving Power Efficiency with an Asymmetric Set-Associative Cache
Zhigang Hu, Stefanos Kaxiras and Margaret Martonosi
79(18)
6.1 Introduction
79(2)
6.2 Related Work
81(3)
6.3 Methodology and Modeling
84(1)
6.4 Asymmetric Set-Associative Cache
85(5)
6.5 Results
90(2)
6.6 Discussion and Future Work
92(2)
6.7 Conclusions
94(1)
References
95(2)
7 Memory Issues in Hardware-Supported Software Safety
Diana Keen, Frederic T. Chong, Premkumar Devanbu, Matthew Farrees, Jeremy Brown, Jennifer Hollfelder and Xiu Ting Zhuang
97(16)
7.1 Introduction
97(1)
7.2 Historical Context
98(2)
7.3 Motivating Applications
100(4)
7.4 Architectural Mechanisms
104(4)
7.5 Results
108(2)
7.6 Conclusions
110(1)
References
111(2)
8 Reconfigurable Memory Module in the RAMP System for Stream Processing
Vason P. Srini, John Thendean and J.M. Rabaey
113(22)
8.1 Introduction
113(2)
8.2 RAMP Architecture
115(2)
8.3 Cluster Architecture
117(2)
8.4 Memory Module Architecture
119(1)
8.5 Datapath Structure
119(4)
8.6 Controller
123(3)
8.7 Handshake Blocks
126(1)
8.8 Scan Chain Register
127(1)
8.9 Design Verification
127(2)
8.10 Conclusion
129(1)
References
130(5)
Part III Software-Based Memory Tuning
9 Performance of Memory Expansion Technology (MXT)
Dan E. Poff, Mohammad Banikazemi, Robert Saccone, Hubertus Franke, Bulent Abali and T. Basil Smith
135(18)
9.1 Introduction
135(2)
9.2 Overview of MXT Hardware
137(2)
9.3 The MXT Memory Management Software
139(1)
9.4 Performance Evaluation
140(8)
9.5 Related Work
148(3)
9.6 Conclusions
151(1)
References
151(2)
10 Profile-Tuned Heap Access
Efe Yardzmci and David Kaeli
153(12)
10.1 Introduction
153(3)
10.2 Related Work
156(1)
10.3 Algorithms
157(4)
10.4 Results
161(1)
10.5 Conclusion
161(1)
References
162(3)
11 Array Merging: A Technique for Improving Cache and TLB Behavior
Daniela Genius, Siddhartha Chatterjee, and Alvin R. Lebeck
165(16)
11.1 Introduction
165(1)
11.2 Related Work
166(2)
11.3 Basic Notions
168(2)
11.4 Cache-conscious Merging
170(3)
11.5 Case study
173(2)
11.6 Experimental Results
175(3)
11.7 Conclusions
178(1)
References
178(3)
12 Software Logging under Speculative Parallelization
Maria Jesús Garzarán, Milos Prvulovic, José Maria Llaberia, Victor Viñals, Lawrence Rauchwerger, and Josep Torrellas
181(18)
12.1 Introduction
181(2)
12.2 Speculative Parallelization and Versioning
183(3)
12.3 Speculation Protocol Used
186(1)
12.4 Efficient Software Logging
187(2)
12.5 Evaluation Methodology
189(2)
12.6 Evaluation
191(1)
12.7 Related Work
192(1)
12.8 Conclusion
193(1)
References
193(6)
Part IV Architecture-Based Memory Tuning
13 An Analysis of Scalar Memory Accesses in Embedded and Multimedia Systems
Osman S. Unsal, Zhenlin Wang, Israel Zoren, C. Mani Krishna, and Csaba Andras Moritz
199(14)
13.1 Introduction and Motivation
199(1)
13.2 Previous Work
200(1)
13.3 Experimental Setup
201(1)
13.4 Results
202(7)
13.5 Conclusion and Future Work
209(1)
References
210(3)
14 Bandwidth-Based Prefetching for Constant-Stride Arrays
Steven O. Hobbs, John S. Pieper, and Stephen C. Root
213(14)
14.1 Introduction
213(1)
14.2 Previous Work
214(1)
14.3 Off-Chip Bandwidth
215(2)
14.4 Cache Conflicts
217(1)
14.5 Algorithm Details
218(4)
14.6 Evaluation
222(2)
14.7 Conclusion
224(1)
References
225(2)
15 Performance Potential of Effective Address Prediction of Load Instructions
Pritap S. Ahúja, Joel Emer, Artur Klauser and Shubhendu S. Mukherjee
227(22)
15.1 Introduction
227(3)
15.2 Effective Address Predictors
230(4)
15.3 Evaluation Methodology
234(4)
15.4 Results
238(4)
15.5 Related Work
242(1)
15.6 Conclusion and Future Work
243(2)
References
245(4)
Part V Workload Considerations
16 Evaluating Novel Memory System Alternatives for Speculative Multithreaded Computer Systems
A.J. Klein Osowski and David J. Lilja (University of Minnesota
249(14)
16.1 Introduction
249(1)
16.2 Background and Motivation
250(1)
16.3 The Superthreaded Architecture Model
251(1)
16.4 Methodology
252(2)
16.5 Results
254(3)
16.6 Conclusion
257(3)
References
260(3)
17 Evaluation of Large L3 Caches Using TPC-H Trace Samples
Jaeheon Jeong, Ramendra Sahoo, Krishnan Sugavanam, Ashwini Nanda and Michel Dubois
263(16)
17.1 Introduction
263(1)
17.2 TPC-H Traces
264(3)
17.3 Evaluation Methodology
267(1)
17.4 Simulation Results
268(6)
17.5 Related Work
274(1)
17.6 Conclusion
275(1)
References
276(3)
18 Exploiting Intelligent Memory for Database Workloads
Pedro Trancoso and Josep Torrellas
279(14)
18.1 Introduction
279(1)
18.2 Related Work
280(1)
18.3 F1exRAM
281(1)
18.4 F1exDB
282(3)
18.5 Experimental Setup
285(2)
18.6 Experimental Results
287(3)
18.7 Conclusion and Future Work
290(1)
References
290(3)
Author Index 293(2)
Subject Index 295

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